Skip Navigation LinksANALOG 2018 Invited Talks

16. GMM/ITG-Fachtagung ANALOG 2018 

Invited Talks 

Invited Talks 


Behavioural Modeling for SoC Simulation: Bridging Analog and Firmware Demands
Presenter: Rainer Findenig, Gabriel Rutsch, Infineon Technologies AG

Simulating today’s SoC models requires fast models of the digital part, the compute platform, and the analog part, in order to be able to efficiently run application software in the simulation.

While abstraction for digital models is well understood, our experience shows that today, the most critical issues are with analog models.

A sensible abstraction is required to achieve models that include all relevant details with the required accuracy, yet still provide the simulation performance required for SoC and firmware verification. At the same time, to reduce development costs, additional focus needs to be placed on maintainability and reusability. In this talk, we show how we addressed this challenge for different SoCs developed at Infineon.

  • Rainer Findenig received his diploma from the Upper Austrian University of Applied Sciences in Hardware/Software Systems Engineering in 2007 and his PhD from Johannes Kepler University Linz in 2016.
  • His PhD research was focused on code generation for efficient models of digital hardware for virtual prototyping.
  • He joined Infineon in 2016 and is currently in charge of virtual prototype development for Infineon’s high-end Radar ICs.
  • Gabriel Rutsch received an MSc degree in Electrical and Computer Engineering from Technical University Munich in 2015.
  • Since then he has been working for Infineon Technologies AG as methodology development and system level design engineer. 
  • His specific field of activity is the methodology development for AMS system modeling and emulation.



Current Sensing Circuits and Applications
Presenter: Misha Ivanov, Texas Instruments Deutschland GmbH

Today, we need to measure current everywhere. In most, if not all electrical systems, it is a key part of managing power. However, the requirements to the measurement of current have vast variation. We need to sense leakages in micro-amps, get to full scale in 100’s of amps, at speed up to 1MHz and the potentials of the current conductor that jump from 0V to 600V in <10ns.

Today not any one solution can do it all.  The industry created a number of technologies and circuit topologies that are used in current sensing.  These include magnetic field sensors measuring down to nano-Tesla; shunts with only a few micro-ohms; signal amplifiers with offset less than 1 microvolt; high-voltage isolation ICs sustaining surges up to 12000V.

This presentation will attempt to provide an overview of system and circuit approaches used to solve the main challenges in several key applications.  We will cover the topologies for precision measurements, solutions to high voltage, common-mode transient immunity, and sensing very high and very low currents.

  • Misha Ivanov holds an M.S.E.E. degree from Ohio State University and has been with Burr-Brown and Texas Instruments since 1997, first in Arizona and from 2001 in Germany.
  • Misha has designed precision linear and mixed signal amplifiers, sensor conditioning circuits and delta-sigma modulators.
  • He holds sixteen patents and was elected TI's Senior Member of Technical Stuff.
  • He currently leads a precision ADC design team, focusing on isolated delta-sigma modulators and amplifiers.



Competitive CMOS RF Transceiver Design
Presenter: Timo Gossmann, Jakob M. Tomasik, Intel Deutschland GmbH

The evolution of modern systems for cellular communication started with GSM is currently moving towards 5G. This is also reflected in the evolution of Intel’s SMARTi(TM) transceiver ICs. Since starting in 2000, our SMARTi-product family has seen a significant transformation in technology, architecture, die size, supported bands and features.

To keep pace and to cope with these ever increasing demands, our development process had to be adapted and optimized, new methodologies and tools had to be developed and very different engineering mindsets had to be aligned. This does not end now, next generation RF transceivers will set even more demanding challenges to comply with requests to meet more stringent KPIs.

In this talk, we will give an impression about the complexity of a state of the art cellular transceiver chip.

We will show what kind of engineering resources and disciplines (e.g. analog, digital, RF and software design) are involved and why their tight cooperation is necessary to map the extremely complex requirements to a successful product operated in modern cellular phones.

  • Timo Gossmann received his diploma in electrical engineering from TU Darmstadt in 1995.
  • As student he was working at Panasonic and worked on the first 100Hz digital signal processing chip sets and started his professional career at SIEMENS semiconductor in Munich when Microelectronics was still on um-scale.
  • Joining embedded DRAM product design group, he was designing full custom and semicustom digital circuits and more ‘analog’ blocks like IO drivers.
  • Lacking some required ingredients for the assigned work packages, he became also involved in synthesis library development and design flow topics.
  • In 1997 he joined SIEMENS semiconductor RF design group, extending his CMOS/digital-centric expertise towards BiCMOS technologies, RF- and mixed signal design.
  • After initially working on car radio applications, he soon transitioned to cellular product development, right before the SMARTi cellular RF transceiver product line activities were started.
  • Since then he actively contributed to design and productization of many SMARTi versions throughout the years with SIEMENS, Infineon and currently Intel.
  • He also held several technical lead and line management positions in Germany and several foreign countries and is currently leading the transmitter sub-project in the next ramping high volume product.
  • Jakob M. Tomasik received his diploma and his PhD degree from the Hamburg University of Technology (TUHH) in 2004 and 2010, respectively.
  • His PhD topic was focused on the research of low-noise and low-power analog circuits for biomedical applications.
  • From 2010 to 2013 he worked as an R&D engineer at EPCOS GmbH & Co. KG, Duisburg, on automotive and industrial microcontroller solutions.
  • In 2013, he joined Intel Deutschland GmbH in Duisburg where he was responsible for the design of RF circuits for cellular products.
  • Since 2017 he is a team lead for RF circuit design at Intel in Munich.




Design Challenges and Methodology Considerations for Highly-Integrated mm-Wave Systems in Silicon-Based Technologies
Presenter: Vadim Issakov, Infineon Technologies

The recent advances in silicon-based semiconductor processes and packaging technologies enable high-level integration of system on chip (SoC) and system in package (SiP) solutions for millimeter-wave (mm-wave) communication or radar applications. These solutions find growing interest due to the increasing demand for a lowest bill of materials. The amount of external components shall be reduced by integrating more and more analog, digital, power management and RF functional blocks on the same chip, on a smallest chip area and at a lowest price. The demonstration of Silicon-Germanium (SiGe) HBT or even CMOS integrated transceiver circuits at millimeter-wave frequencies has given rise to the sales volumes of classical and emerging applications.

As the level of complexity of the highly-integrated systems rises, chip, package and PCB parasitic effects play an ever increasing role on the overall system performance. Any coupling mechanisms that involve off-chip signaling can be easily overlooked, unless full 3D environment in the vicinity of the RF circuit is considered. Hence, it is insufficient to model the interconnect parts separately and concatenate the models, as some coupling effects might not be captured fully. Additionally, amount of inductors and transformers in highly integrated mm-wave transceivers is steadily increasing with the growing complexity of the chips. Driven on one hand by higher integration, yet on the other hand by the demand for cost and chip area reduction, inductors need to be placed densely close to each other resulting in unwanted coupling. Another dominant coupling mechanism is via the substrate. This causes unwanted interferences coupled between different parts of the integrated system, resulting in SNR degradation, reduced data rates and nonlinear distortion effects, as e.g. blocker desensitization.  Therefore, it is necessary to model accurately on-chip coupling paths and include these effects in circuit simulation during design stage. However, extraction and simplification of chip, package and PCB layout features to make it usable for EM simulation, poses a major challenge in complex designs.

This talk focusses on design considerations of highly-integrated mm-wave transceiver chipsets in silicon-based technologies. The speaker will discuss circuit design considerations and challenges related to critical building blocks. Particularly, high sensitivity of key performance parameters to layout parasitics at mm-wave frequencies is discussed. Additionally, challenges related to accurate extraction of parasitics are addressed. Next, chip-package-PCB co-design and co-simulation methodology by means of accurate EM modelling for RF systems is presented. Furthermore, crosstalk mechanisms related to coupling between integrated inductors/transformer and coupling via substrate at mm-wave frequencies are discussed. Finally, examples of mm-wave radar and communication systems at frequencies above 60 GHz are presented.

  • Vadim Issakov was born in the Russian Federation in 1981.
  • He received M.Sc. degree (cum laude) in microwave engineering from the Technical University of Munich and Ph.D. degree from the University of Paderborn, Germany (summa cum laude) in 2006 and 2010, respectively.
  • He is a principal engineer for mm-wave circuit design at Infineon Technologies AG in Neubiberg, Germany.
  • He is a technical lead of a research group working on mm-wave circuit design in CMOS and SiGe technologies for radar and communication applications.

Improving Test Coverage and Eliminating Test
Escapes Using Analog Defect Analysis 
Presenter: Walter Hartong, Art Schaldenbrand, Vladimir Zivkovic, Cadence Design Systems, Munich

Complex systems, like cars or planes, place significant demands on the designers of the many sub components integrated into the system. If a single sub components does not perform to specification, then the entire system’s operation is compromised. As an example of the challenge, consider a typical mid class automobile. It may contain 80 Electronic Control Modules, ECU, each containing several ICs. If the failure rate of the ICs averages 1 defective part per million, 1 dppm, then over 1 % of the cars will fail coming off the assembly line. Consequently, the system integrators are pushing their suppliers to provide parts with a goal of 0 dppm, 0 defective parts. How can IC company achieve this level of quality? While the analog and mixed-signal components are the leading source of test escapes that result in field failures, up to 95% of the field returns are due to the analog or mixed-signal elements in a design. The lack of tools to analyze the test coverage during design has made it difficult for designers to analyze test coverage. As a result, manufacturing test has become the critical step in the flow for ensuring quality. More testing means higher quality; however, more tests mean more test time. Test costs represent a significant portion of the die recurring cost creating a difficult trade-off, increase cost in the hope of increasing quality. To resolve this trade-off, requires more attention on optimizing the test program and testability early in the design cycle.

Analog fault simulation has been proposed for many years, but the technology has not widely adopted to date. The lack of standard analog fault models and a standard methodology for reporting coverage have proved to be a challenge when trying to evaluate ability of test to identify bad parts. The solution has been to refine the problem. Defect-oriented test has been proposed as a solution. Instead of undefinable analog faults, manufacturing defects are modeled and their effect on the circuit performance at test is is simulated. Defect oriented test evaluates the ability of the test program to identify and eliminate manufacturing defects. It is used with traditional analog testing of parametrics and functionality to assure that the structure of the die is also correct. 

Currently the IEEE P2427 Working Group is standardizing this methodology and new tools and simulation environments – like Cadence® Legato™ Reliability Solution – become available commercially.

Moving forward the related functional safety question will influence the analog working environment significantly. 


  • Walter Hartong studied Electrical Engineering/Microelectronics at the University of Hannover.
  • He worked as a research assistant at the Institute of Microelectronic Systems and finished his PhD in Computer Science in 2002.
  • Since 2002, he has been with Cadence Design Systems in Munich, initially as application engineer. His current role is Product Engineering Architect focusing on analog simulation environment and verification.
  • He is one of the core drivers in the ADE Verifier development and contributes to Explorer and Assembler as well. Walter is also interested in mixed-signal topics, analog fault simulation and behavioral modeling.

Cognitive Sensing: What does this mean for us?
Presenter: Josef Sauerer, Fraunhofer-Institute for Integrated Circuits IIS, Erlangen

Originally, a sensor converts a physical quantity at its environmental side into an electrical signal either displayed to an observer or transmitted to control units taking signals from one or more sensors to make decisions. The signal is a direct representation of the physical quantity or state at the sensor’s environmental side.
In many today’s applications we have smart or intelligent sensors, more complex systems comprising the primary sensing element, analog circuitries i.e. for excitation control, compensation and analog signal conditioning, analog-to digital converter, digital information processing and digital communication interface. They often provide support for various modes of operation and interfacing and can take some predefined actions or calculations. Smart sensors can locally extract information from measured input data and transmit the information when necessary, thus reducing network requirements and complexity of central processing units.

Cognitive sensors deploy a number of different input values for acquiring situated information of the sensed environment. They are equipped with additional capabilities based on machine learning processes. This enables cognitive sensors to build up empirical knowledge from their environment. They can work out particular patterns and trends from the signals. Cognitive sensor systems do not just capture measurement values. They analyze them directly, take decisions locally by intelligent interpretations and decide when it is necessary to pass on information or to trigger actions locally.

Thus, cognitive sensing extends »intelligent sensors« by employing sensor fusion and machine learning approaches to solve complex sensing tasks and to bring sensed information in a context. In other words, cognitive sensors do not only provide information but rather already give interpretations what the information really means.

This presentation will give examples of how cognitive sensor systems enable digital transformation to be realized in different application areas: Self-learning approaches can extend possibilities in magnetic position sensing; multimodal sensor fusion combined with machine learning based data evaluation helps properly brushing teeth, analyzing a driver’s emotions or even enabling a digital representation of human sensory perceptions.

  • Josef Sauerer received his diploma in electrical engineering from Friedrich Alexander University Erlangen Nuremberg in 1985.
  • He started his professional career as analog IC designer at the Fraunhofer Institute for Integrated Circuits IIS in Erlangen
  • For some years he was leading a group designing fast analog-to-digital converters in III/V technologies
  • In 1993 he became head of the department for analog IC design with main focus on development of mixed signal ASICs for industrial and automotive applications
  • For some years he was responsible for all IC-design activities at Fraunhofer IIS covering CMOS integrated sensor systems, RF-ICs, mixed signal ICs and digital ICs
  • Currently Josef Sauerer is heading the division of Smart Sensing and Electronics comprising IC design, optical and hall-sensor systems, imaging systems and medical technologies


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