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16. GMM/ITG-Fachtagung ANALOG 2018 


Wednesday, 12th September 2018
Venue - Tutorial

Technical University of Munich, Arcisstr. 21,
80333 Munich, Germany

Seminar room 2999


Maps in different resolution to locate this room can be found here:


How to find TUM - download map


The most convenient way to get there is

  • to enter the inner courtyard of the TUM city campus from Theresienstraße (or Gabelsberger Straße).
  • In the center of the courtyard you can see a silver box-shaped building with two doors.
  • Take the right door and the elevator to floor "2".
  • Leave the elevator and turn to the left.
  • At the end of the corridor you will find seminar room 2999.


Wednesday, 12th September 2018 - Schedule

13:00 Registration, Coffee                                                                                   


13:30  Tutorial A: "Analog Coverage - yesterday's dreams, today's reality and tommorrow's capabilities"                                             
Walter Hartong, Cadence, Munich, Germany
Lars Hedrich, University of Frankfurt, Frankfurt/Main, Germany
Markus Olbrich, University of Hanover, Hannover, Germany

Analog circuits are constantly growing in complexity.
Hence, the verification environment needs to include various input voltages, output loads, temperature ranges or process variations. Many special verification tasks are mandatory, like statistical analysis, EM/IR, reliability analysis, post layout simulation.

Simultaneously, the requirements on verification quality are increasing drastically - the ISO26262 norm for automotive is the most popular example in this trend. The time to market pressure requires even the consumer market to demand strict verification quality goals. A re-spin of a large SOC due to an analog failure is not acceptable anymore.

Beside the classical interactive verification approach, more formalized techniques, verification planning, and completeness and quality metrics are required. Here the concept of "verification coverage" can help to enhance the verification quality and efficiency.

In this tutorial, we will present the latest trends from the EDA industry, namely Cadence Virtuoso ADE Verifier with its new capability to do coverage driven verification for analog circuit. We will see how this can be used in re-live projects even today.
In addition, the academic driven view on analog coverage is presented. The latter stems in parts from the ANCONA project focusing on analog coverage approaches.

Main part of the tutorial will be live demos and hands-on experience in the context of possible coverage measures, a practical view on existing measures and methodologies. Some new approaches to measure coverage and combine the results in an overall coverage view. The whole tutorial will be accompanied by concrete results on small and middle size examples circuits.

  • Walter Hartong studied Electrical Engineering/Microelectronics at the University of Hannover.
  • He worked as a research assistant at the Institute of Microelectronic Systems and finished his PhD in Computer Science in 2002.
  • Since 2002, he has been with Cadence Design Systems in Munich, initially as application engineer.
  • His current role is Product Engineering Architect focusing on analog simulation environment and verification.
  • He is one of the core drivers in the ADE Verifier development and contributes to Explorer and Assembler as well.
  • Walter is also interested in mixed-signal topics, analog fault simulation and behavioral modeling.
  • Lars Hedrich received the Diploma degree in electrical engineering in 1992 and the Ph.D. in 1997 from the University of Hannover and became a junior professor at the same University in 2002.
  • Since 2004 he has been full professor at the Institute of Computer-Science, University of Frankfurt, and head of the design methodology group at the same institute.
  • His research interests include several areas of analog design automation: symbolic analysis of linear and nonlinear circuits, behavioral modeling, reliability analysis and design, circuit synthesis, and formal verification.
  • Markus Olbrich received his Dipl.-Ing. and Dr.-Ing. degrees from Leibniz University of Hannover in 1996 and 2005, respectively.
  • He is now with the Institute of Microelectronic Systems in Hannover as group leader since 2001 and Academic Director since 2010.
  • His research interests cover mixed-signal verification methods including formal verification and he also works on physical design methods.




16:00 Tutorial B: "Advances in worst case and yield Analysis for circuit design"

Michael Pronath, MunEDA, Munich, Germany

In this tutorial we will review a statistical worst case analysis methodology for designers of analog/RF/digital full custom circuits, which includes operating conditions such as temperature or Vdd, aging, as well as random variation of the manufacturing process.

We will discuss its mathematical background, accuracy and efficiency, demonstrate recent algorithmic improvements of worst case analysis software, together with applications of high sigma statistical analysis to analog/RF circuits and to large regular circuit structures such as memory arrays. 

  • Michael Pronath has extensive experience in statistical analysis, modeling, and optimization.
  • Prior to founding MunEDA, Michael worked as a research assistant at the Institute for Electronic Design Automation at the Technical University of Munich.
  • He holds a PhD in Electrical Engineering from the Technical University of Munich as well as an MBA of University of Hagen.
  • Dr. Pronath is author and coauthor of several international publications on methods of analog integrated circuit design and testing of mixed-signal circuits.
17:00 End


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