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Key Notes EMLC 2011  

Key Notes EMLC 2011  


The Photomask Technology Roadmap:  Hydra or Hyperbole? 




 Christopher Progler

 Chief Technology Officer

 Photronics Inc.






Like the seven heads of the Hydra, challenges driving the photomask roadmap seem to strike from many directions often coming into view with razor precision and little real warning.  Moreover, when one challenge seems to wane (e.g., haze) another similar problem can return with twice the intensity.  On the other hand, despite strong ongoing arguments of insurmountable obstacles (economic to technical), it appears our modestly sized photomask industry has kept pace with the technology needs of the user.  In fact, it is hard to identify major yield loss challenges or broad roadmap impediments that are driven by a lack of photomask technology even for advanced nodes.  


In this talk, we will explore the roadmap from both points of view.  First, the need to drive down parallel paths of technology, from inverse masks to EUV, will be addressed and this will naturally lead to a discussion on photomask equipment cost and capability as potential show stoppers for a viable and healthy mask industry.  We will consider ways to extract a maximum value from invested equipment with primary focus on how an understanding of the image quality can be leveraged to improve the model.  From the other end, we will look at trends that can potentially change the way technology is applied on photomasks such as more pervasive use of simple grating structures or economic and technical trends that could lead to photomask roadmap retraction from the user demand side. 



Advanced Lithography: More than Rayleigh



Foto Bert Koek

  Bert Koek

  Senior Vice President

  of Lithography Applications,






Lithography, the key enabling factor in semiconductor device shrink, is driving advances in patterning and overlay. The k1 factor in Lord Rayleigh’s equation, R = k1λ/NA, has been a synonym for patterning complexity for many decades.

Next to shorter wavelength and higher NA, technology developments in imaging enhancement enabled a lower k1 factor to further improve resolution. Besides resolution, the layer-to-layer overlay determines the minimum possible cell size of the device, and the complexity of the overlay challenges has increased together with the complexity of the patterning challenges.

With 1.35 NA ArF-immersion as the last traditional optical lithography solution, more enhanced lithography techniques are needed to support the shrink roadmap. The applications roadmap for patterning and overlay needs to consider use of restricted design layouts, source mask optimization, 3D mask effects, double patterning methods, system to system matching, application specific tuning, and last but not least stability control for both scanner and process.

The transition from ArF-I to EUV reduces some of the imaging enhancement and overlay complexity. Given the NA roadmap and the resolution requirements, k1 factors of greater than 0.35-0.4 are possible. However with the introduction of EUV, new imaging challenges are introduced. Mask shadowing effects, long range stray light, and thin resists will require additional new technology to be developed to support EUV patterning in high volume manufacturing.

The paper will show how these challenges should be addressed consistently from design implementation to manufacturing control.



The Metamorphosis of a Mask Shop - How Foundry Requirements Change Mask Making



Foto Schmidt


  Thomas Schmidt

   General Manager

   Advanced Mask Technology, Dresden






A mask house traditionally driven primarily by high end memory and CPU demands has to change not only its technical but also in its logistical structures when being transferred to foundry dominated operation.
The AMTC is undergoing such a transition since April 2010. In this talk we show the impact of such a transition in terms of cost, cycle time and logistics requirements as well as the number of technology node processes to be covered.

We will focus not only on the key performance parameters placement and dimension control, but also on data volume in data preparation, writing and inspection.






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